In signal transmission, the range of a terminal resistor at a transmitting end and at a receiving end, for example, 50 ohm ±10%, is set as a standard for impedance matching.
However, depending on absolute precision of the resistance value of a resistor element in LSI fabrication, such as ±15%, there are cases where difficulties are encountered in observing the prescribed range in designing.
Further, since the resistance value is changed with temperature or with lapse of time, there is a possibility that the resistance value of a resistance, which was within the prescribed range at ambient temperature, departs from the prescribed range at lower or higher temperatures. Hence, an impedance adjustment circuit is needed in order to keep a terminal resistor at a constant value.
The role of the impedance adjustment circuit includes a circuit comparing an external resistor with a resistor under adjustment, provided in an LSI, to control a setting code for the terminal resistor so that terminal resistor will be of a desired resistance value.
If the setting code to the resistor under adjustment is fully fixed, there is a possibility that its resistance value becomes offset with temperature, with change in the power supply voltage or with lapse of time. It is therefore necessary to monitor the resistance value for all time. In case the resistance value becomes offset from the desired value, the setting code needs to be updated automatically. However, if the setting code is changed every so often, jitter is generated in the transmission signal waveform. Thus, the setting code needs to be leveled so as not to change the setting code too frequently.
FIG. 27 shows a configuration of the impedance adjustment circuit disclosed in Patent Document 1. Referring to FIG. 27, the impedance adjustment circuit includes a comparator 1013 that compares a voltage 1011a, divided by an external resistor 1012 and a replica resistor 1011, having a variable resistance value, with a reference voltage (REFV). If it is the resistance value of the replica resistor 1011 that is larger, the divided voltage 1011a becomes lower. In this case, the comparator 1013 outputs an Up/Dn signal which is “H” (High). If conversely the replica resistor 1011 is lower, an Up/Dn signal which is “L” (Low) is output.
If the Up/Dn signal is “H”, an up-down counter 1014 increments the count state at a CLK timing. If conversely the Up/Dn signal is “L”, the up-down counter decrements the counter state. The counter state, expressed by three bits in the example of FIG. 27, is output to a code conversion circuit 1015 and to an averaging circuit 1016.
The code conversion circuit 1015 provides a resistor setting code, corresponding to the input counter state, to the replica resistor 1011. In the example of FIG. 27, the resistor setting code has a width of seven bits.
In a steady state, if the count value (counter state) of the up-down counter 1014 is “3”, the UP/Dn signal becomes “H”. The UP/Dn signal becomes “L” for the next state “4” and then reverts to the state “3”. This sequence is repeated. That is, the state change shown in FIG. 29 occurs in succession.
If the state of alternate occurrences of the count values (counter states) “3” and “4” of the up-down counter 1014 is converted to a setting signal for the terminal resistor to be adjusted, and used in the so converted state, there is generated unwanted jitter in the transmission signal waveform.
The averaging circuit 1016 holds and averages past n counter states to produce the so averaged state to suppress variations in the counter state.
Referring to FIG. 28, the averaging circuit 1016 that takes an average value of the past four counter states includes three-bit synchronization circuits 10161 to 10164, operating circuits 101621 to 101623 for averaging the counter states, and a synchronization circuit 101651 for timing adjustment.
The averaging circuit 1016 is configured so that, in case the average value of the past n counter states is such thatX≦average value<X+1where X is an integer, X will be output, as the decimal part is truncated.
If the internal state of the up-down counter 1014 is a repetition of “3”, “4” and “3” and so forth, in this order, the average value is “3.5”, and a output of the averaging circuit 1016 is a constant value of “3” (see FIG. 30).
In similar manner, if the inner state of the up-down counter 1014 is a repetition of “3”, “4”, “5”, “4”, “3” and so forth, in this order, the average value is “4”. The output of the averaging circuit 1016 is a constant value of “4” (see FIG. 32).
This stable state signal is delivered to another code conversion circuit 1017 which generates a setting signal to a terminal resistor as a target for adjustment. Since the state signal delivered is stabilized by the averaging circuit 1016, the setting signal output may be freed of variations.
[Patent Document 1] JP Patent Kokai Publication JP-P2004-32721A